MSP430 Assembly Paul Roper

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1 MSP430 Assembly Paul Roper
Finish this lecture before Blinky Lab is due Paul Roper

2 Topics to Cover… Double Operand Instructions
Single Operand Instructions Jump Instructions Emulated Instructions MSP430 Assembly Program High Level vs. Assembly Assembly Code BYU CS/ECEn 124 MSP430 Assembly Paul Roper

3 Levels of Transformation
Problems Algorithms Language (Program) Programmable Assembly Instructions Machine (ISA) Architecture Computer Specific Microarchitecture Manufacturer Specific Circuits Devices BYU CS/ECEn 124 MSP430 Assembly

4 How are we going to proceed?
Problems Algorithms 5. C Language Language (Program) Programmable 1. Assembly Language 2. ISA Machine (ISA) Architecture Computer Specific 3. Machine Code Micro-architecture Manufacturer Specific 4. Micro Architecture Circuits Devices BYU CS/ECEn 124 MSP430 Assembly

5 Assembly language program Machine language programs
Compilation Algorithm The assembly language stage is often skipped… by hand C-language program c = a + b; compiler However, low-level assembly language is often used for programming directly. We will start from assembly language but use high-level C language to help understand it. Assembly language program ADD r4,r5 assembler Machine language programs Compiler often directly generates machine code. to machine for execution BYU CS/ECEn 124 MSP430 Assembly

6 MSP 430 Micro-Architecture
Address Bus Memory Address Register Program Counter Source Operand Instruction Register Destination Operand Port 1 Output Arithmetic Logic Unit Condition Codes Memory BYU CS/ECEn 124 MSP430 Assembly Data Bus

7 MSP 430 Data Storage The MSP430 CPU has 64KB memory space and 16 registers for data storage R0 (PC) – Program Counter This register always points to the next instruction to be fetched R1 (SP) – Stack Pointer The MSP430 CPU stores the return address of routines or interrupts on the stack User programs store local data on the stack R2 (SR/CG1) – Status Register The status of the MSP430 CPU is defined by a set of bits contained in register R2 BYU CS/ECEn 124 MSP430 Assembly

8 MSP 430 Registers R2 (SR/CG1), R3 (CG2) – Constant Generators
Six different constants commonly used in programming can be generated using the registers R2 and R3, without adding a 16-bit extension word of code to the instruction Register As Constant Remarks R2 00 - Register mode 01 (0) Absolute mode 10 00004h +4, bit processing 11 00008h +8, bit processing R3 00000h 0, word processing 00001h +1 00002h +2, bit processing 0FFFFh -1, word processing BYU CS/ECEn 124 MSP430 Assembly

9 MSP 430 Registers R4-R15 – General Purpose registers
The general purpose registers R4 to R15 can be used as data registers, data pointers and indices. They can be accessed either as a byte or as a word Instruction formats support byte or word accesses The status bits of the CPU in the SR are updated after the execution of a register instruction. BYU CS/ECEn 124 MSP430 Assembly

10 Format I: 12 Double Operand Instructions
Mnemonic Operation Description Arithmetic instructions ADD(.B or .W) src,dst src+dstdst Add source to destination ADDC(.B or .W) src,dst src+dst+Cdst Add source and carry to destination DADD(.B or .W) src,dst src+dst+Cdst (dec) Decimal add source and carry to destination SUB(.B or .W) src,dst dst+.not.src+1dst Subtract source from destination SUBC(.B or .W) src,dst dst+.not.src+Cdst Subtract source and not carry from destination Logical and register control instructions AND(.B or .W) src,dst src.and.dstdst AND source with destination BIC(.B or .W) src,dst .not.src.and.dstdst Clear bits in destination BIS(.B or .W) src,dst src.or.dstdst Set bits in destination BIT(.B or .W) src,dst src.and.dst Test bits in destination XOR(.B or .W) src,dst src.xor.dstdst XOR source with destination Data instructions CMP(.B or .W) src,dst dst-src Compare source to destination MOV(.B or .W) src,dst srcdst Move source to destination BYU CS/ECEn 124 MSP430 Assembly

11 Examples MOV.w #0x08,R5 ; move source to destination
; assign a hexadecimal value 0x08 to Register R5 AND.w #0x00,R6 ; bitwise AND source with destination ; whatever value in R6 is ANDed with 0 -> R6=0 ADD.w #0x03,R6 ; add source to destination ; R6 = R6+3 = 0+3 = 3 SUB.w R6, R5 ; subtract source from destination ; R5 = R5-R6 = R5+(Not R6)+1 = 8-3 = 5 XOR.w R6, R5 ; bitwise XOR source with destination ; R5 = 0011 XOR 0101 = 0110 = 6 BIC.w #0x03, R5 ; clear bits in destination ; (Not 0011) AND 0110 = 1100 AND 0110 = 0100 = 4 BIS.w #0x08, R5 ; set bits in destination ; 1000 OR 0100 = 1100 = 12 BIT.w #0x08, R5 ; test bits in destination ; 1000 AND 1100 = > Bit 3 is not zero CMP.w R6, R5 ; compare source to destination ; R5-R6 = 12-6 = 6 greater than 0, so R5 > R6 Good questions for test BYU CS/ECEn 124 MSP430 Assembly Paul Roper

12 Format II: 7 Single Operand Instructions
Mnemonic Operation Description Logical and register control instructions RRA(.B or .W) dst MSBMSB… LSBC Roll destination right RRC(.B or .W) dst CMSB…LSBC Roll destination right through carry SWPB( or .W) dst Swap bytes Swap bytes in destination SXT dst bit 7bit 8…bit 15 Sign extend destination PUSH(.B or .W) src SP-2SP, Push source on stack Program flow control instructions CALL(.B or .W) dst SP-2SP, dstPC Subroutine call to destination RETI Return from interrupt BYU CS/ECEn 124 MSP430 Assembly

13 Examples MOV.w #0xF009,R5 ; move source to destination
; assign a hexadecimal value 0x08 to Register R5 RRA.w R5 ; Roll destination right and send LSB to Carry ; > C=1 RRC.w R5 ; Roll destination right through Carry ; > C=0 SWPB.w R5 ; subtract source from destination ; > SXT R5 ; sign extension ; > ; (bit 7 is 1) bits 8~15 are all set to 1 PUSH, CALL, and RETI will be discussed later Good questions for test BYU CS/ECEn 124 MSP430 Assembly Paul Roper

14 Jump Instruction Format
Jump Instructions Jump Instruction Format Jump instructions are used to direct program flow to another part of the program. The condition on which a jump occurs depends on the Condition field consisting of 3 bits: JNE/JNZ : jump if not equal JEQ/JZ : jump if equal JNC/JLO : jump if carry flag equal to zero JC/JHS : jump if carry flag equal to one JN : jump if negative (N = 1) JGE : jump if greater than or equal (N = V) JL : jump if lower (less) (N  V) JMP : unconditional jump (no condition check) BYU CS/ECEn 124 MSP430 Assembly

15 Examples MOV.w #0x05,R5 ; move source to destination
; assign a hexadecimal value 0x05 to Register R5 MOV.w #0x03,R6 ; move source to destination ; assign a hexadecimal value 0x03 to Register R6 CMP.w R6, R5 ; compare source to destination ; R5-R6 = 5-3 = 2 greater than 0, so R5 > R6 JNE somewhere ; jump if not equal ; The program will jump to “somewhere” because R5 ≠ R6 Good questions for test BYU CS/ECEn 124 MSP430 Assembly Paul Roper

16 Emulated Instructions
In addition to the 27 instructions of the CPU there are 24 emulated instructions The CPU coding is unique The emulated instructions make reading and writing code easier, but do not have their own op-codes Emulated instructions are replaced automatically by CPU instructions by the assembler There are no penalties for using emulated instructions. BYU CS/ECEn 124 MSP430 Assembly

17 Emulated Instructions
Mnemonic Operation Emulation Description Arithmetic instructions ADC(.B or .W) dst dst+Cdst ADDC(.B or .W) #0,dst Add carry to destination DADC(.B or .W) dst dst+Cdst (decimally) DADD(.B or .W) #0,dst Decimal add carry to destination DEC(.B or .W) dst dst-1dst SUB(.B or .W) #1,dst Decrement destination DECD(.B or .W) dst dst-2dst SUB(.B or .W) #2,dst Decrement destination twice INC(.B or .W) dst dst+1dst ADD(.B or .W) #1,dst Increment destination INCD(.B or .W) dst dst+2dst ADD(.B or .W) #2,dst Increment destination twice SBC(.B or .W) dst dst+0FFFFh+Cdst dst+0FFhdst SUBC(.B or .W) #0,dst Subtract source and borrow /.NOT. carry from dest. BYU CS/ECEn 124 MSP430 Assembly

18 Emulated Instructions
Mnemonic Operation Emulation Description Logical and register control instructions INV(.B or .W) dst .NOT.dstdst XOR(.B or .W) #0(FF)FFh,dst Invert bits in destination RLA(.B or .W) dst CMSBMSB-1 LSB+1LSB0 ADD(.B or .W) dst,dst Rotate left arithmetically (multiplied by 2) RLC(.B or .W) dst LSB+1LSBC ADDC(.B or .W) dst,dst Rotate left through carry Program flow control BR dst dstPC MOV dst,PC Branch to destination DINT 0GIE BIC #8,SR Disable (general) interrupts EINT 1GIE BIS #8,SR Enable (general) interrupts NOP None MOV #0,R3 No operation RET @SPPC SP+2SP Return from subroutine BYU CS/ECEn 124 MSP430 Assembly

19 Emulated Instructions
Mnemonic Operation Emulation Description Data instructions CLR(.B or .W) dst 0dst MOV(.B or .W) #0,dst Clear destination CLRC 0C BIC #1,SR Clear carry flag CLRN 0N BIC #4,SR Clear negative flag CLRZ 0Z BIC #2,SR Clear zero flag POP(.B or .W) dst @SPtemp SP+2SP tempdst MOV(.B or Pop byte/word from stack to destination SETC 1C BIS #1,SR Set carry flag SETN 1N BIS #4,SR Set negative flag SETZ 1Z BIS #2,SR Set zero flag TST(.B or .W) dst dst + 0FFFFh + 1 dst + 0FFh + 1 CMP(.B or .W) #0,dst Test destination BYU CS/ECEn 124 MSP430 Assembly

20 Example: Emulated Instructions
Emulated instructions are replaced automatically by CPU instructions by the assembler Could be replaced differently Clear the contents of register R5: Increment the content of register R5: Decmrent the content of register R5: CLR R5 = MOV.W #0, R5 INC R5 = ADD.W #1, R5 DEC R5 = SUB.W #1, R5 BYU CS/ECEn 124 MSP430 Assembly

21 Example: Emulated Instructions
Decrement by two the contents of register R5: Do not carry out any operation: Add the carry flag to the register R5: DECD R5 = SUB.W #2, R5 NOP = MOV.W R3, R3 ADC R5 = ADC.W #0, R5 BYU CS/ECEn 124 MSP430 Assembly

22 Source Addressing Modes
The MSP430 has four basic modes for the source address: Rs - Register x(Rs) - Indexed Register @Rs - Register Indirect (not for destination) @Rs+ - Indirect Auto-increment (not for destination) In combination with registers R0-R3, three additional source addressing modes are available: label - PC Relative, x(PC) &label – Absolute, x(SR) #n – (not for destination) BYU CS/ECEn 124 MSP430 Assembly

23 Destination Addressing Modes
There are two basic modes for the destination address: Rd - Register x(Rd) - Indexed Register In combination with registers R0/R2, two additional destination addressing modes are available: label - PC Relative, x(PC) &label – Absolute, x(SR) BYU CS/ECEn 124 BYU CS/ECEn 124 Chapter 6 - MSP430 Micro-Architecture MSP430 Assembly 23

24 Addressing Modes Register Mode (Rn) The most straightforward addressing mode and is available for both source and destination Example: mov.w r5,r6 ; move word from r5 to r6 The registers are specified in the instruction; no further data is needed Also the fastest mode and does not require an addition cycle Byte instructions use only the lower byte, but clear the upper byte when writing 1 Op-code S-reg Ad b/w As D-reg BYU CS/ECEn 124 MSP430 ISA

25 Addressing Modes Indexed Mode x(Rn) The address is formed by adding a constant (index) to the contents of a CPU register Example: mov.b 3(r5),r6 ; move byte from ; M(310+r5) to r6 Indexed addressing can be used for source and/or destination, value in r5 is unchanged. The index is located in the memory word following the instruction and requires an additional memory cycle There is no restriction on the address for a byte, but words must lie on even addresses 1 Op-code S-reg Ad b/w As D-reg BYU CS/ECEn 124 MSP430 ISA

26 Symbolic Mode (PC Relative)
Addressing Modes Symbolic Mode (PC Relative) The address if formed by adding a constant (index) to the program counter (PC) Example: (mov.w x(PC), r6 where x=Cnt-PC) mov.w Cnt,r6 ; move word ; M(Cnt) or M(x+PC) to r6 The PC relative index is calculated by the assembler Produces position-independent code, but rarely used in the MSP430 because absolute addressing can reach all memory addresses Note: this is NOT an appropriate mode of addressing when referencing fixed locations in memory such as the special function registers (SFR’s) 1 Op-code S-reg Ad b/w As D-reg BYU CS/ECEn 124 MSP430 ISA

27 Absolute Mode (&label)
Addressing Modes Absolute Mode (&label) The address is formed directly from a constant (index) and specified by preceding a label with an ampersand (&) Example: (mov.w x(SR), r6 where 0 is used for SR) mov.w &Cnt,r6 ; move word ; M(Cnt) to r6 Same as indexed mode with the base register value of 0 (by using the status register SR as the base register) The absolute address is stored in the memory word following the instruction and requires an additional cycle Note: this is the preferred mode of addressing when referencing fixed locations in memory such as the special function registers (SFR’s) 1 Op-code S-reg Ad b/w As D-reg BYU CS/ECEn 124 MSP430 ISA

28 Indirect Register Mode (@Rn)
Addressing Modes Indirect Register Mode The address of the operand is formed from the contents of the specified register Example: ; move word ; M(r5) to r6 Only available for source operands Same as indexed mode with index equal to 0, but does not require an additional instruction word The value of the indirect register is unchanged 1 Op-code S-reg Ad b/w As D-reg BYU CS/ECEn 124 MSP430 ISA

29 Indirect Autoincrement Mode (@Rn+)
Addressing Modes Indirect Autoincrement Mode The address of the operand is formed from the contents of the specified register and afterwards, the register is automatically increment by 1 if a byte is fetched or by 2 if a word is fetched Example: ; move word ; M(r5) to r6 ; increment r5 by 2 Only available for source operands. Usually called post-increment addressing. Note: All operations on the first address are fully completed before the second address is evaluated 1 Op-code S-reg Ad b/w As D-reg BYU CS/ECEn 124 MSP430 ISA

30 Immediate Mode (#n) mov.w #100,r6 ; 100 -> r6
Addressing Modes Immediate Mode (#n) The operand is an immediate value Example r6) mov.w #100,r6 ; 100 -> r6 The immediate value is located in the memory word following the instruction Only available for source operands The immediate mode of addressing is a special case of auto-increment addressing that uses the program counter (PC) as the source register. The PC is automatically incremented after the instruction is fetched; hence points to the following word 1 Op-code S-reg Ad b/w As D-reg BYU CS/ECEn 124 MSP430 ISA

31 Examples - Source registers memory 0010 000F 0020 0010 9000 0011 9004
label: 0012 9006 0013 mov.w R5, R ; move the content of R5 (0010) to R6 R ; use the content of R7 (9000) as the address to move data (000F) to R8 mov.w &0x9004, R6 ; go to the absolute address (9004) to move data (0011) to R6 mov.w 2(R7), R9 ; use the content of R7 (9000) as the base address and offset it by 2 (9002) to move data (0010) to R9 mov.w &0x9006, R5 ; go to the absolute address (9006) to move data (0012) to R5 R6 ; use the content of R7 (9000) as the address to move data (000F) to R6 and then increment R7 by 2 (one word is 2 bytes) mov.w #0x9000, R7 ; move the immediate value (9000) to R7 mov.w label, R ; move the data (0012) in the memory space represented by “label” to R7 BYU CS/ECEn 124 MSP430 Assembly

32 Examples - Destination
registers memory 0010 000F R5 R6 R7 R8 R9 x9000 x9002 x9004 x9006 x9008 0020 0010 9000 0011 9004 label: 0012 9006 0013 mov.w R5, R ; move the content of R5 (0010) to R6 mov.w R5, 4(R7) ; use the content of R7 (9000) as the base address and offset it by 4 (9004) and move the content of R5 (0010) to the effective address (9004) mov.w R6, label ; move the content of R6 (0012 moved from R5) to the memory space represented by “label” mov.w &0x9004, &0x ; go to the absolute address (9004) to move data (0011) to the memory location of the absolute address (9008) mov.w R6, &label ; move the content of R6 (0012 moved from R5) to the memory space represented by the absolute address “label” BYU CS/ECEn 124 MSP430 Assembly

33 High Level vs. Assembly High Level Languages Assembly Languages
More programmer friendly More ISA independent Each high-level statement translates to several instructions in the ISA of the computer Assembly Languages Lower level, closer to ISA Very ISA-dependent Each instruction specifies a single ISA instruction Makes low level programming more user friendly More efficient code BYU CS/ECEn 124 MSP430 Assembly

34 High Level vs. Assembly Why Assembly Code? Allows us to work at a slightly higher level than machine language. Allows us to use symbolic names for opcodes Allows us to use symbolic names for memory locations - SUM, PRODUCT Don’t need to know every address of every storage location. Calculates addresses for us – really a big deal! Helps to allocate memory locations. Provides additional error checking BYU CS/ECEn 124 MSP430 Assembly

35 The first assembly program
;******************************************************************************* ; MSP430 Micro-Architecture Simulator Code; ; Description: ; Display an incrementing counter in the simulator LEDs. ; MSP430 ; ; | | ; | P1.0|-->RED LED ; | P1.1|-->YELLOW LED ; | P1.2|-->BLUE LED ; | P1.3|-->GREEN LED ;******************************************************************************* cdecls C,LIST, "msp430x22x4.h" ; .text ; Program reset RESET: mov.w #0x0300,SP ; Initialize stack pointer mov.w #WDTPW+WDTHOLD,&WDTCTL ; Stop WDT bis.b #0x0f,&P1DIR ; Set P1.0-3 output mov.w #0,r14 Mainloop: mov.b r14,&P1OUT ; output P1.0-3 inc.w r14 and.w #0x000f,r ; mask counterWait: mov.w Delay,r ; Delay to R15 push r15 L1: dec.w 0(sp) ; decrement delay counter jnz L ; delay over? mov.w @sp+,r ; y jmp Mainloop ; repeat Delay: word 2 .sect ".reset" ; MSP430 RESET Vector .short RESET ; NMI .end Output Pins to control the LEDs Comments Instructions Directives Labels Comments Directives BYU CS/ECEn 124 MSP430 Assembly

36 What does it do? Move an immediate value #0x0300 into stack pointer register SP (R1) Move an immediate value that is the OR’ed result of WDTPW and WDTHOLD (both are predefined memory addresses) into a memory location at the absolute address WDTCTL (also a predefined address) Set the lowest 4 bits of the value stored in the absolute address location P1DIR to all ‘1’. This is to set Pins 0~3 of Port 1 to be for output controls (turn LEDs on or off) Move an immediate value 0 to register # is actually created by hardware RESET: mov.w #0x0300,SP ; Initialize stack pointer mov.w #WDTPW+WDTHOLD,&WDTCTL ; Stop WDT bis.b #0x0f,&P1DIR ; Set P1.0-3 output mov.w #0,r14 Mainloop: mov.b r14,&P1OUT ; output P1.0-3 inc.w r14 and.w #0x000f,r ; mask counterWait: mov.w Delay,r ; Delay to R15 push r15 L1: dec.w 0(sp) ; decrement delay counter jnz L ; delay over? mov.w @sp+,r ; y jmp Mainloop ; repeat Delay: .word 2 Move the value stored in register #14 to the absolute address location PIOUT (predefined for Port 1 output register) Increment value in register #14 by 1 AND the value in register #14 with 0x000F ( ) to keep only the lowest 4 bits in r14. Move a value “Delay” to r15 Move the value in r15 onto the stack .word directive assigned a work value 2 to Delay If the previous instruction result is NOT zero, then jump to location labeled L1, else continue to the next instruction Move the value stored on top of the stack to r15 and then increment SP by 2 Decrement the value stored on top of the stack Unconditionally (always) jump to location labeled Mainloop BYU CS/ECEn 124 MSP430 Assembly

37 mov.w #0x0300,SP ; Initialize stack pointer
Immediate mode Register mode Absolute mode RESET: mov.w #0x0300,SP ; Initialize stack pointer mov.w #WDTPW+WDTHOLD,&WDTCTL ; Stop WDT bis.b #0x0f,&P1DIR ; Set P1.0-3 output mov.w #0,r14 Mainloop: mov.b r14,&P1OUT ; output P1.0-3 inc.w r14 and.w #0x000f,r ; mask counterWait: mov.w Delay,r ; Delay to R15 push r15 L1: dec.w 0(sp) ; decrement delay counter jnz L ; delay over? mov.w @sp+,r ; y jmp Mainloop ; repeat Delay: .word 2 Label (PC relative) mode Indexed register mode Indirect auto-increment mode BYU CS/ECEn 124 MSP430 Assembly

38 Three Basic Constructs
Coding Assembler Three Basic Constructs BYU CS/ECEn 124 MSP430 Assembly

39 if-then-else Translation
Coding Assembler if-then-else Translation Could be different addressing modes cmp.w #1,&buzzerON ; jne myElse ; xor.b #0x20,&P4OUT ; bis.b #0x02,&P1OUT ; jmp myNext ; myElse: ; bic.b #0x02,&P1OUT ; ; myNext: ; if (buzzerON == 1) { pulse_buzzer(); turn_on_LED(); } else turn_off_LED(); If a > b? Subtask 1 Subtask 2 n y BYU CS/ECEn 124 MSP430 Assembly

40 while Translation ; #define TRUE 1 while_loop: ; bit.w #1,R4 ;
Coding Assembler while Translation ; while_loop: ; bit.w #1,R ; jnz while_done ; call #LED_ON ; call #delay ; call #LED_OFF ; jmp while_loop ; while_done: ; #define TRUE 1 while (TRUE) { LED_ON(); delay(); LED_OFF(); } BYU CS/ECEn 124 MSP430 Assembly

41 for-loop Translation .bss i,2 ; int i; mov.w #0,&i ;
Coding Assembler for-loop Translation .bss i, ; mov.w #0,&i ; fl_ck: cmp.w #10,&i ; jge for_done ; call #do_dot ; call #delay ; call #do_dash ; add.w #1,&i ; jmp fl_ck ; for_done: ; int i; for(i=0; i<10; i++) { do_dot(); delay(); do_dash(); } BYU CS/ECEn 124 MSP430 Assembly

42 switch/case Translation
Coding Assembler switch/case Translation switch/case cmp.w #DOT,&myByte ; jne sw_ ; call #do_dot ; jmp sw_end ; sw_01: cmp.w #DASH,&myByte ; jne sw_end ; call #do_dash ; ; sw_end: ; switch (myByte) { case DOT: do_dot(); break; case DASH: do_dash(); default: } BYU CS/ECEn 124 MSP430 Assembly

43 Systematic Decomposition
IDEA Step by Step Procedure Finiteness Must terminate. Definiteness Each step is precisely stated. Effective Computability Each step can be carried out. BYU CS/ECEn 124 MSP430 Assembly

44 Stepwise Refinement Also known as incremental development.
Systematic Decomposition Stepwise Refinement Also known as incremental development. Start with problem statement: “Write an assembler program for a traffic stop light.” Decompose task into a few simpler subtasks. Turn on the green LED for 5 seconds. Blink the green LED on and off at 1 second intervals for 6 seconds (3 offs and 3 ons). Blink the green LED on and off at 0.25 second intervals for 4 seconds (8 offs and 8 ons). And finally, turn the green LED off for 10 seconds. Repeat the process of dividing into subtasks until you get to the machine instruction level. BYU CS/ECEn 124 MSP430 Assembly

45 F2013 Blinky Example BYU CS/ECEn 124 MSP430 Assembly
;******************************************************************************* ; CS/ECEn 124 Lab 4 - blinky.asm: Software Toggle P1.0 .cdecls C,LIST, "msp430x20x3.h" ; MSP430F2013 ; .text ; beginning of executable code RESET: mov.w #0x0280,SP ; init stack pointer mov.w #WDTPW+WDTHOLD,&WDTCTL ; stop WDT bis.b #0x01,&P1DIR ; set P1.0 as output mainloop: xor.b #0x01,&P1OUT ; toggle P1.0 mov.w #0,r ; use R15 as delay counter delayloop: dec.w r ; delay over? jnz delayloop ; n jmp mainloop ; y, toggle led ; Interrupt Vectors .sect ".reset" ; MSP430 RESET Vector .short RESET ; start address .end BYU CS/ECEn 124 MSP430 Assembly

46 Add 2nd Delay Loop (not enough)
;******************************************************************************* ; CS/ECEn 124 Lab 4 - blinky.asm: Software Toggle P1.0 .cdecls C,LIST, "msp430x20x3.h" ; MSP430F2013 delay set 0 ; .text ; beginning of executable code RESET: mov.w #0x0280,SP ; init stack pointer mov.w #WDTPW+WDTHOLD,&WDTCTL ; stop WDT bis.b #0x01,&P1DIR ; set P1.0 as output mainloop: xor.b #0x01,&P1OUT ; toggle P1.0 mov.w #delay,r ; use R15 as delay counter delayloop: dec.w r ; delay over? jnz delayloop ; n r15 goes in negative immediately and ; will stop when it wraps around and returns to 0 delay2: dec.w r15 ; repeat the same loop one more time jnz delay2 jmp mainloop ; y, toggle led ; Interrupt Vectors .sect ".reset" ; MSP430 RESET Vector .short RESET ; start address .end BYU CS/ECEn 124 MSP430 Assembly

47 Blinky Lab Need two loops, one outer loop and one inner loop to get enough delay for 10 second interval delay set ; be careful what numbers you choose delay set mainloop: xor.b #0x01,&P1OUT ; toggle P1.0 mov.w #delay1,r ; use R15 as outer loop delay counter Need a double loop here to increase the total delay time BYU CS/ECEn 124 MSP430 Assembly

48 Cycles Per Instruction...
Instruction Timing Cycles Per Instruction... Src Dst Cycles Length Example Rn Rm MOV R5,R8 @Rm MOV x(Rm) ADD R5,4(R6) EDE XOR R8,EDE &EDE MOV R5,&EDE #n x(Rm) MOV #100,TAB(R8) &TONI &EDE MOV &TONI,&EDE See “How To Determine Cycles Per Instruction...” in Blinky Lab instructions. BYU CS/ECEn 124 MSP430 Assembly

49 Include Symbolic & Absolute Address
Include #N Include Symbolic & Absolute Address Include Symbolic & Absolute Address Include Symbolic & Absolute Address Include Symbolic & Absolute Address BYU CS/ECEn 124 MSP430 Assembly

50 Instruction Timing 4 cycles 1 cycle 1 cycle 2 cycles 2 cycles
mainloop: xor.b #0x01,&P1OUT ; toggle P1.0 mov.w #0,r ; use R15 as delay counter delayloop: dec.w r ; delay over? jnz delayloop ; n jmp mainloop ; y, toggle led 2 cycles 2 cycles BYU CS/ECEn 124 MSP430 Assembly

51 LEDs A light-emitting diode (LED) is a semiconductor light source
Device: LED LEDs A light-emitting diode (LED) is a semiconductor light source When a diode is forward biased (switched on), electrons are able to recombine with holes within the device, releasing energy in the form of photons BYU CS/ECEn 124 MSP430 Assembly

52 LEDs 6 LED’s on eZ430X Development Board P1.0 Red LED eZ430-RF2500
Device: LED LEDs 6 LED’s on eZ430X Development Board P1.0 Red LED eZ430-RF2500 P1.1 Green LED eZ430-RF2500 P2.6 LED #1 (Green) P2.7 LED #2 (Orange) P3.3 LED #3 (Yellow) P4.6 LED #4 (Red) BYU CS/ECEn 124 MSP430 Assembly

53 Device: LED LEDs Port bits must be enabled for output by writing a 1 to the port direction register bis.b #0x03,&P1DIR ; eZ430-RF2500 LED's bic.b #0xc0,&P2SEL ; select GPIO bis.b #0x40,&P2DIR ; LED #1 (P2.6) bis.b #0x80,&P2DIR ; LED #2 (P2.7) bis.b #0x08,&P3DIR ; LED #3 (P3.3) bis.b #0x40,&P4DIR ; LED #4 (P4.6) 1 Pin# 1 Pin# BYU CS/ECEn 124 MSP430 Assembly

54 LEDs Turn LED off by writing a 0 to the port pin
Device: LED LEDs Turn LED off by writing a 0 to the port pin bic.b #0x03,&P1OUT ; eZ430-RF2500 LED's bic.b #0x40,&P2OUT ; LED #1 (P2.6) bic.b #0x80,&P2OUT ; LED #2 (P2.7) bic.b #0x08,&P3OUT ; LED #3 (P3.3) bic.b #0x40,&P4OUT ; LED #4 (P4.6) Turn LED on by writing a 1 to the port pin bis.b #0x03,&P1OUT ; eZ430-RF2500 LED's bis.b #0x40,&P2OUT ; LED #1 (P2.6) bis.b #0x80,&P2OUT ; LED #2 (P2.7) bis.b #0x08,&P3OUT ; LED #3 (P3.3) bis.b #0x40,&P4OUT ; LED #4 (P4.6) Toggle LED by XOR’ing a 1 to the port pin xor.b #0x03,&P1OUT ; eZ430-RF2500 LED's xor.b #0x40,&P2OUT ; LED #1 (P2.6) xor.b #0x80,&P2OUT ; LED #2 (P2.7) xor.b #0x08,&P3OUT ; LED #3 (P3.3) xor.b #0x40,&P4OUT ; LED #4 (P4.6) BYU CS/ECEn 124 MSP430 Assembly

55 BYU CS/ECEn 124 MSP430 Assembly